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Intel's NetBurst Architecture
The Pentium 4 is using what Intel calls their "NetBurst" architecture, which is replacing the aging P6 architecture mentioned above. Don't be fooled by the name, however, as the architecture has nothing to do with increasing the speed of the 'net. What it is, however, is a set of technical features that allow the processor to perform better in the long run.
I'm not going to go into detail regarding each of the parts of the NetBurst architecture as it's well beyond the scope of this article, but it's basically comprised of four major features.
The first, Hyper Pipelined Technology, is basically a name for how the Pentium 4 has twice the number of pipeline stages than the Pentium III does, 20 to 10, respectively. By increasing the number of stages, it means that the processor can do less work per clock and, thus, will allow the clock speed to be pushed up. Using this method does allow for higher-clocked processors, but it also means a lot of penalties in terms of performance per clock. The idea behind Hyper Pipelined Technology, therefore, is that, eventually, the higher clocked processors will make up for the performance lost with the longer pipeline.
The second and third features, Rapid Execution Engine and Execution Trace Cache, are, in essence, engineering tricks to make up for some of the performance lost by the Hyper Pipelined Technology.
The fourth and final feature of the NetBurst architecture is in the form of a 400MHz (!!) system bus, compared with only 100 MHz-266MHz that we see with other processors. The Pentium 4 is using an ATGL+ bus, which actually runs at 100MHz, but is quad-pumped, making it effectively 400MHz. This is much like how the Athlon's EV6 bus is double-pumped. I'm not exactly sure how they managed to quad-pump the thing, but it sure is impressive!
I will be coming back to the chipset and bus used for the Pentium 4 later on in another part where we look at the motherboard.
On to: SSE2
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